Low cost wafer box improvements

ABSTRACT

The wafer box includes a tray ( 10 ) and a cover ( 62 ). The tray ( 10 ) includes an inner ( 34, 36, 38, 40 ) and outer ( 24, 26, 28, 30 ) wall configuration with horizontal semicircular channels ( 48, 50, 52, 54 ) therebetween to perform spacing, strengthening and horizontal shock-absorbing functions. The tray ( 10 ) further includes a wafer cavity ( 42 ) formed within the inner wall ( 34, 36, 38, 40 ). The wafer cavity ( 42 ) includes a lattice ( 46 ) of ridges on the floor thereof to provide a vertical shock absorbing function. The wall ( 76, 78, 80, 82 ) of the cover ( 62 ) engages and mates to the outer wall ( 24, 26, 28, 30 ) of the tray ( 10 ) thereby forming a double wall configuration. A pedestal configuration ( 90, 92 ) is formed on the corners and mid-spans of the top of the cover ( 62 ) to provide standoff clearance between the inter-stacked boxes to minimize or eliminate the transmission of shock and vibration through an inter-stack configuration.

This application claims priority from provisional application Ser. No.60/515,869, filed Oct. 29, 2003.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a containment device or wafer box fortransporting semiconductor wafers, particularly utilizing thermoformedmaterial in place of other transport wafer packaging systems utilized inshipping wafers from a front-end wafer fabrication facility to aback-end product manufacturing facility.

2. Description of the Prior Art

The prior art contains a variety of designs for the containment andtransport of semiconductor wafers. These designs must provide bothelectrostatic and mechanical protection for the wafers containedtherein. Preferably, such containment devices should be easily adaptableto various automated apparatus which load or unload the semiconductorwafers. Such containment devices should have a simple design which isreliable and economical to mass produce. Additionally, such containmentdevices should be compliant to industry standards to achieve equipmenthandling capability.

Examples of some prior art are U.S. Pat. No. 6,193,068 entitled“Containment Device for Retaining Semiconductor Wafers” issued on Feb.27, 2001 to Lewis et al.; U.S. Pat. No. 6,286,684 entitled “ProtectiveSystem for Integrated Circuit (IC) Wafers Retained Within ContainersDesigned for Storage and Shipment” issued on Sep. 11, 2001 to Brooks etal.; U.S. Pat. No. 6,003,674 entitled “Method and Apparatus for PackingContaminant-Sensitive Articles and Resulting Package” issued on Dec. 21,1999 to Brooks; and U.S. Pat. No. 5,724,748 entitled “Apparatus forPackaging Contaminant-Sensitive Articles and Resulting Package” issuedon Mar. 10, 1998 to Brooks et al.

OBJECTS AND SUMMARY OF THE INVENTION

In order to attain the above and other objects, the wafer box of thepresent invention includes a bottom floor attachment design whichmechanically isolates wafers from side walls thereby acting as a shockabsorber against vertical impact and vibration; a side wallconfiguration which isolates interior walls and the cavity fromhorizontal shock impact; a pedestal configuration at the corners andmid-span which provides standoff clearance when full boxes areinter-stacked so that shock and vibration are not transmitted throughthe inter-stack configuration; a side wall configuration comprised ofmating surfaces from the lid and bottom to create a double thicknesswall thereby allowing substantially increased stacking capabilities;interlocking engagement elements on four sides to provide fullengagement and survival of multiple drops of fully loaded wafer boxes(typically including 16 semiconductor wafers); interlocked offsetflanges to provide for simple separation of the base from the lid; alarge side wall flat surface to provide for the attachment of a largelabel along the side of the wafer box; and translucent material alongthe top of the wafer box so that large print paperwork is visiblethrough the top of the box in order to reduce or eliminate the need foradditional labels around the box.

Optionally, the wafer box can include a side wall collapsibleconfiguration through engagement of the lid to the base interface. Thiscould be accomplished either by the vertical insertion of the lid overthe base or through a living hinge folding action of the lid around thebase. This provides for the reduction of excess movement of thesemiconductor wafers in the cavity of the wafer box.

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects and advantages will become apparent from the followingdescription and from the accompanying drawings, wherein:

FIG. 1 is a top plan view of the tray of the wafer box of the presentinvention.

FIG. 2 is a side plan view of the tray of the wafer box of the presentinvention.

FIG. 3 is a front plan view of the tray of the wafer box of the presentinvention.

FIG. 4 is a perspective view of the tray of the wafer box of the presentinvention.

FIG. 5 is a top plan view of the cover of the wafer box of the presentinvention.

FIG. 6 is a side plan view of the cover of the wafer box of the presentinvention.

FIG. 7 is a front plan view of the cover of the wafer box of the presentinvention.

FIG. 8 is a perspective view of the cover of the wafer box of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the drawings in detail wherein like numerals indicatelike elements throughout the several views, one sees from FIGS. 1-4 thatthe tray 10 of the wafer box of the present invention includes a planarbase 12 which is square or rectangular in shape, as bounded by sides 14,16, 18, 20. Side 20 includes an indented area 22. Indented area 22, incombination with a similar indented area on the cover as will bedescribed hereinafter in more detail, provides the opportunity for theuser, or even automated machinery, to separate easily the tray 10 fromthe cover. Outer walls 24, 26, 28, 30 rise inwardly adjacent from sides14, 16, 18, 20, respectively, and terminate in elevated planar ledgearea 32. Inner walls 34, 36, 38, 40 extend from the interior of elevatedplanar ledge area 32 to planar base 12 thereby forming wafer cavity 42therewithin.

Outer walls 24, 26, 28, 30 include semi-circular downwardly taperedconcave portions 44 which add to the rigidity of the outer walls.Furthermore, the portion of planar base 12 within wafer cavity 42includes lattice 46 of ridges thereby mechanically isolating any wafers(not shown) within wafer cavity 42 from inner walls 34, 36, 38, 40 andacting as a shock absorber against vertical impact and vibration.

Similarly, horizontal semi-circular channels 48, 50, 52, 54 are formedbetween respective outer walls 24, 26, 28, 30 and inner walls 34, 36,38, 40. Channels 48, 50, 52, 54 perform spacing, strengthening andhorizontal shock-absorbing functions.

A pair of detent dimples 60 is formed on each of outer walls 24, 26, 28,30 at about the one quarter and three quarters position along the spanof each of the outer walls.

One sees from FIGS. 5-8 that cover 62 of the wafer box includes lowerrim 64 bounded by sides 66, 68, 70, 72 which generally correspond to thefootprint of base 12 of tray 10. However, side 72 includes indented area74 which is intended to be laterally offset from indented area 22 whenside 72 of cover 62 is aligned with side 20 of tray 10. That is, whenviewed from the perspective of FIGS. 4 and 8, indented area 22 is on theleft portion of side 20 while indented area 74 is on the right portionof side 72. This forms an interlocked offset flange configuration whichallows the user to grasp sides 20 and 72 between a thumb and forefingerand disengage cover 62 from tray 10 with a simple twisting motion.

Cover side walls 76, 78, 80, 82 rise from lower rim 64 and terminate incover upper planar surface 83. Cover upper planar surface 83 may beformed of translucent material so that (large print) printed materialinside may reduce the need for labeling of the wafer box. Cover sidewalls 76, 78, 80, 82 are shaped so as to be able to outwardly engageouter walls 24, 26, 28, 30 when cover 62 is placed over tray 10 therebyforming a double thickness outer wall configuration. Cover side walls76, 78, 80, 82 include semi-circular downwardly tapered concave portions84 which outwardly engage and mate to semi-circular downwardly taperedconcave portions 44 of tray 10 in the installed position. Central planarlabel areas 86 are formed at a central portion of each of cover sidewalls 76, 78, 80, 82, between the two interior semicircular concaveportions 84.

A pair of detent dimples 88 is formed on each of cover side walls 76,78, 80, 82 at about the one quarter and three quarters position alongthe span of each of the cover side walls. When cover 62 is installedover tray 10, detent dimples 88 of cover 62 extend into detent dimples60 of tray 10 thereby forming a detent relationship.

Corner pedestals 90 rise from the intersections of the cover side walls76, 78, 80, 82 while mid-span pedestals 92 rise from the mid-point ofcover side walls 76, 78, 80, 82. Pedestals 90, 92 provide standoffclearance when full wafer boxes are inter-stacked so that transmissionof shock and vibration through the inter-stack configuration isminimized or eliminated.

Tray 10 and cover 62 are typically formed of thermoformed material,although those skilled in the art will recognize a range of equivalentsafter review of this disclosure.

To use the resulting wafer box, semiconductor wafers (not shown) areloaded into wafer cavity 42 of tray 10. Cover 62 is then placedvertically over tray 10 so that detent dimples 88 of cover 62 extendinto detent dimples 60 of tray 10 thereby forming a detent relationship,semi-circular downwardly tapered concave portions 84 of cover 62outwardly engage and mate to semi-circular downwardly tapered concaveportions 44 of tray 10, and indented areas 22 and 74 are laterallyoffset from each other thereby forming an interlocked offset flangeconfiguration.

Thus the several aforementioned objects and advantages are mosteffectively attained. Although a single preferred embodiment of theinvention has been disclosed and described in detail herein, it shouldbe understood that this invention is in no sense limited thereby and itsscope is to be determined by that of the appended claims.

1. A container for semiconductor wafers, comprising: a tray elementincluding a planar base, outer side walls rising from said planar base,inner side walls formed inwardly adjacent from said outer side walls andforming a wafer containment area therewithin, and lateral shockingabsorbing means formed between said inner side walls and said outer sidewalls; and a cover element including a planar top and cover side wallsextending from said planar top wherein, when said cover element isengaged with said tray element, said cover side walls are outwardlyadjacent from said outer walls of said tray element.
 2. The containerfor semiconductor wafers of claim 1 wherein said outer side wallsinclude first semi-circular concave portions and said cover side wallsinclude second semicircular concave portions wherein, when said coverelement is engaged with said tray element, said first semi-circularconcave portions engage said second semi-circular concave portions. 3.The container for semiconductor wafers of claim 2 wherein said first andsecond semi-circular concave portions are downwardly tapered.
 4. Thecontainer for semiconductor wafers of claim 1 wherein said lateral shockabsorbing means comprises channels formed between respective said innerside walls and said outer side walls.
 5. The container for semiconductorwafers of claim 4 wherein said channels are formed by wallsperpendicular to said inner side walls and said outer side walls.
 6. Thecontainer for semiconductor wafers of claim 5 wherein said channels aresemi-circular.
 7. The container for semiconductor wafers of claim 1wherein said planar base includes protrusions which form lower shockabsorbing means.
 8. The container for semiconductor wafers of claim 7wherein said protrusions form a lattice of ridges.
 9. The container forsemiconductor wafers of claim 1 wherein said cover side walls terminatein a rim, said rim including a portion which is parallel to said planartop.
 10. The container for semiconductor wafers of claim 9 wherein, whensaid cover element is engaged with said tray element, said rim abutswith a portion of said planar base outward from said outer side walls.11. The container for semiconductor wafers of claim 10 wherein said rimincludes first indented areas and wherein said planar base outward fromsaid outer side walls includes second indented areas.
 12. The containerfor semiconductor wafers of claim 11 wherein said first indented areasare offset from said second indented areas thereby forming aninterlocked offset flange configuration facilitating the separation ofsaid cover element from said tray element.
 13. The container forsemiconductor wafers of claim 1 wherein said outer side walls includefirst detent elements and said cover side walls include second detentelements wherein, when said cover element is engaged with said trayelement, said first detent elements engage said second detent elements.14. The container for semiconductor wafers of claim 13 wherein saidfirst detent elements and said second detent elements are dimples. 15.The container for semiconductor wafers of claim 1 wherein said planartop includes offset elements to offset the container from a successiveupper container.
 16. The container for semiconductor wafers of claim 15wherein said offset elements include pedestal elements formed on saidplanar top at intersections of said cover side walls.
 17. The containerfor semiconductor wafers of claim 15 wherein said offset elementsinclude pedestal elements formed on said planar top at mid-spans of saidcover side walls.
 18. The container for semiconductor wafers of claim 1wherein at least a portion of said planar top is translucent.
 19. Thecontainer for semiconductor wafers of claim 1 wherein said cover sidewalls include central planar label areas.
 20. The container forsemiconductor wafers of claim 1 wherein said tray element and said coverelement are formed of thermoformed plastic.